Pulse shaping and clock data recovery for multi-gigabit standard compliant 60 GHz digital radio

This paper presents the first ultra low power (5 mW) multi-gigabit pulse-shaping filter and clock data recovery circuits fully integrated in a 90-nm CMOS wireless digital radio meeting the specifications of 60 GHz wireless standards. The architecture features a 4.4 Gsps capable 13-tap FIR pulse shap...

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Bibliographic Details
Published in2010 IEEE MTT-S International Microwave Symposium p. 1
Main Authors Barale, F., Iyer, G. B., Perumana, B. G., Sen, P., Sarkar, S., Rachamadugu, A., Dudebout, N., Pinel, S., Laskar, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2010
Subjects
Clocks
CMOS digital integrated circuits
Digital communication
Digital filters
Finite impulse response filter
Frequency
Jitter
Pulse circuits
Pulse shaping methods
Transceivers
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Summary:This paper presents the first ultra low power (5 mW) multi-gigabit pulse-shaping filter and clock data recovery circuits fully integrated in a 90-nm CMOS wireless digital radio meeting the specifications of 60 GHz wireless standards. The architecture features a 4.4 Gsps capable 13-tap FIR pulse shaping filter on the TX side, and a dual loop clock data recovery on the RX side to suppress the high frequency jitter introduced by the pulse shaping. Using a fully integrated 60 GHz TDD transceiver embedding the presented solution, a 95% reduction of the high frequency jitter has been measured at the standard nominal 1.728 Gbps data rate. The solution features a minimal power overhead of 5 mW from 1 V voltage supply.
ISBN:1424460565
9781424460564
ISSN:0149-645X
2576-7216
DOI:10.1109/MWSYM.2010.5517513