A Multiplier-Accumulator Macro for a 45 MIPS Embedded RISC Processor

This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point is to utilize a multiplier array and the Booth's encoder twice in a cycle. This multiplier-accumulator can execute one multiply-add operation (32bit multiplication followed by 6...

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Bibliographic Details
Published inESSCIRC '95: Twenty-first European Solid-State Circuits Conference pp. 174 - 177
Main Authors Yano, Naoka, Ootaguro, Yukio, Sugeno, Yukio, Ueno, Maki, Muroya, Yukinori, Aramaki, Tsuneo
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.1995
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Summary:This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point is to utilize a multiplier array and the Booth's encoder twice in a cycle. This multiplier-accumulator can execute one multiply-add operation (32bit multiplication followed by 64bit addition) per cycle at 50MHz. The area is 2.35mm 2 with 0.4μm CMOS technology.
ISBN:2863321803
9782863321805