A study on channel design for 0.1 /spl mu/m buried p-channel MOSFETs

• Published in: IEEE transactions on electron devices Vol. 43; no. 11; pp. 1942 - 1949
• Main Authors: Shamarao, P., Ozturk, M.C.
• Format: Journal Article
• Language: English
• Published: IEEE 01.11.1996
• Subjects: Capacitance; Degradation; Design optimization; Doping; Electrodes; Fabrication; Light scattering; MOSFET circuits; Temperature; Transconductance
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.543031

This paper investigates the channel design for buried p-channel MOSFETs with an effective channel length of 0.1 /spl mu/m via simulations using the two-dimensional device simulator PISCES IIB. A new three-layer design is considered with the objective of obtaining low junction capacitance while maintaining high current drive and suppressing punchthrough. The channel design consists of a p-type layer under the gate oxide, an n-type anti-punchthrough layer below the p-type layer followed the substrate with a doping concentration of 1e17/cm/sup 3/. By optimizing the doping structure, an attempt is made to investigate fundamental limits of the buried channel design. In concurrence with published results, it is shown that there is a maximum allowable thickness for the first layer, while the thickness of the anti-punchthrough layer has a minimum value in order to effectively suppress punchthrough. The above constraints enable devices with good subthreshold characteristics (subthreshold swing <90 mV/Dec) as well as high transconductance which is a matter of concern for ultra-thin buried layers. While simulation results show that it is possible to fabricate buried p-channel MOSFETs with n-type polysilicon gate electrodes in the 0.1 /spl mu/m regime, it is also evident that advanced doping and low temperature fabrication technologies are needed that provide control over doped layers of ultra-thin dimensions.