A cache-based message passing scheme for a shared-bus multiprocessor

• Published in: [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings pp. 358 - 364
• Main Authors: Preiss, B.R., Hamacher, V.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1988
• Subjects: Hardware; Message passing; Software systems
• ISBN: 9780818608612; 0818608617
• DOI: 10.1109/ISCA.1988.5246

A scheme for using cache-based hardware to provide simple and efficient message-passing support for message-based software systems on a tightly-coupled, shared-bus multiprocessor is described. This approach is based on the utilization of the existing interprocessor communications medium, the shared bus, to effect the exchange of single-word messages. Communication between processes is accomplished over logical channels using simple, blocking send and receive primitives. The physical processor/channel interface is designed so that the message transfer primitives can be implemented as single machine instructions, namely store and fetch. Special-purpose caches, called message caches, mediate channel operations and effect the exchange of messages over the shared bus.< >