A review of logic synthesis techniques for beginning VHDL designers

The electronics industry has adopted hardware description languages (HDLs) as a method to manage complex application specific integrated circuit (ASIC) designs. However, ambiguous code and inappropriate usage of HDL syntax may restrict an IC design engineer's ability to fully exploit the advant...

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Bibliographic Details
Published inProceedings of SOUTHEASTCON '96 pp. 541 - 544
Main Authors Bien, Y.K., Perry, R.J., Arora, K.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
Application specific integrated circuits
Computer aided engineering
Counting circuits
Design engineering
Educational institutions
Electronics industry
Engineering management
Hardware design languages
Integrated circuit synthesis
Logic design
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Summary:The electronics industry has adopted hardware description languages (HDLs) as a method to manage complex application specific integrated circuit (ASIC) designs. However, ambiguous code and inappropriate usage of HDL syntax may restrict an IC design engineer's ability to fully exploit the advantages offered by HDLs and logic synthesis tools. This paper briefly reviews many common mistakes made by beginning VHDL designers and provides several suggestions for improving their coding techniques.
ISBN:9780780330887
0780330889
DOI:10.1109/SECON.1996.510131