PESE: an efficient partition-based electrical simulation environment

• Published in: 38th Midwest Symposium on Circuits and Systems. Proceedings Vol. 1; pp. 57 - 60 vol.1
• Main Authors: Kim, Y.G., Dharchoudhury, A., Kang, S.M., Kim, K.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1995
• Subjects: Analytical models; Circuit simulation; Circuit testing; Computational modeling; Convergence; Equations; Logic gates; SPICE; Timing; Very large scale integration
• ISBN: 9780780329720; 0780329724
• DOI: 10.1109/MWSCAS.1995.504377

Due to the performance limitations of electrical level circuit simulators, the number of design circuits that cannot be analyzed but need to be simulated at the electrical level are increasing. Hence, extensive research has been carried out with the aim of improving simulation performance for large and complex circuits. This paper introduces a new environment for electrical level simulation with high performance. PESE uses circuit partitioning based on the channel connectedness, in conjunction with a standard electrical simulator like SPICE, to provide a greater simulation speed with less memory requirement while maintaining the desired level of electrical accuracy. The size of circuits PESE can handle is not limited, and the speedup is expected to grow with the circuit size while having much less memory space requirement. Several benchmark circuits have been tested and the results show that PESE provides accurate simulation capability with a speed and memory space advantage.