Perfect Planar Technology for VLSIs

For high packing density in LSI, some surface planarization techniques for field isolation, gate and multilevel metallization structures have been offered(1,2,3). The purpose of this paper is to provide a new fabrication process for a semiconductor device with a planer surface and higher packing den...

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Bibliographic Details
Published in1982 Symposium on VLSI Technology. Digest of Technical Papers pp. 30 - 31
Main Authors Ehara, Kohei, Morimoto, Takashi, Muraumoto, Susumu, Hosoya, Tetsuo, Matsuo, Seitaro
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.1982
Subjects
Cyclotrons
Etching
Fabrication
Large scale integration
Plasma applications
Plasma properties
Resists
Semiconductor devices
Substrates
Very large scale integration
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Summary:For high packing density in LSI, some surface planarization techniques for field isolation, gate and multilevel metallization structures have been offered(1,2,3). The purpose of this paper is to provide a new fabrication process for a semiconductor device with a planer surface and higher packing density.