Solid-II; High-Voltage, High-Gain Ka-Channel-Length CMOSFETs Using Silicide with Selfaligned Ultra-Shallow (3S) Junction

One of the notorious limitations in realization of kA-channel-length CMOSFETs is the formation of ultra-shallow p^+junction as thin as 0.1 μm or less with low sheet resistance. Another problem with down-scaled devices, such as a conventional LDD (Lightly Doped Drain) device, is the drastic reduction...

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Bibliographic Details
Published in1985 Symposium on VLSI Technology. Digest of Technical Papers pp. 56 - 57
Main Author Horiuchi, Masatada
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.1985
Subjects
Boron
CMOSFETs
Conductivity
Contact resistance
Laboratories
Measurement errors
Silicidation
Silicides
Surface resistance
Temperature
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Summary:One of the notorious limitations in realization of kA-channel-length CMOSFETs is the formation of ultra-shallow p^+junction as thin as 0.1 μm or less with low sheet resistance. Another problem with down-scaled devices, such as a conventional LDD (Lightly Doped Drain) device, is the drastic reduction in current gain despite miniaturization and excellent high breakdown voltage properties. This paper describes a novel pile-up phenomenon leading to an available layered structure of Silicide with a Selfaligned Ultra-Shallow (3S) junction. This new structure significantly improves device performances and reduces constraints when applied to submicron channel length (L eff > 0.2μm) CMOFETs.
ISBN:4930813093
9784930813091