Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach

• Published in: APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems pp. 1107 - 1111
• Main Authors: Khaled, P., Chowdhury, M.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2006
• Subjects: Capacitance; Capacitors; Electromagnetic modeling; Integrated circuit noise; Integrated circuit packaging; Noise level; Power engineering and energy; Power engineering computing; Power supplies; Semiconductor device noise
• ISBN: 9781424403875; 9781424403868; 1424403871; 1424403863
• DOI: 10.1109/APCCAS.2006.342315

This paper investigates the challenges and limitations of existing techniques of handling power bus modeling, power supply noise, and the usage of decoupling capacitor at the chip and package levels. One major aspect of the existing works is that handling of these issues at the package and at the chip levels are addressed in two separate phases by two separate groups. Considering the package-chip co-design reality for very high performance integrated circuits in future, it is more effective to tackle all these issues together in one working phase rather than trying to resolve each at a time. This ensures more efficient design by providing options to trade off noise tolerance, number and location of decoupling capacitors, silicon resource used by decoupling, and design limitations for power bus modeling. This paper attempts to identify the common issues that need to be resolved at both package and chip level. It also points out where the existing technology stands, what are the challenges and limitations of existing methodologies and techniques, and what are the options to improve the efficiency of analysis and handling of power supply noise at both levels