Fully-parallel multi-megabit integrated CAM/RAM design

Previous implementations of large-capacity Content Addressable Memories (CAMs) have employed advanced fabrication techniques or serialized operation. This paper describes a more generally applicable fully-parallel solution based on circuit and architectural innovation. A "pre-classified" C...

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Bibliographic Details
Published inProceedings of IEEE International Workshop on Memory Technology, Design, and Test pp. 46 - 51
Main Authors Schultz, K.J., Gulak, P.G.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1994
Subjects
Associative memory
CADCAM
Circuit simulation
Circuit testing
Computer aided manufacturing
Fabrication
History
Random access memory
Read-write memory
Technological innovation
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Summary:Previous implementations of large-capacity Content Addressable Memories (CAMs) have employed advanced fabrication techniques or serialized operation. This paper describes a more generally applicable fully-parallel solution based on circuit and architectural innovation. A "pre-classified" CAM is integrated into the same array as its target RAM, and both use the same core cells. Architecture and operation are described, as are two critical-path circuits: the match-line pull-down and the multiple match resolver. An 8 kb test chip is described, and simulation results for a 1 Mb configuration are presented.< >
ISBN:9780818662454
081866245X
DOI:10.1109/MTDT.1994.397198