High speed sub-halfmicron flash memory technology with simple stacked gate structure cell

• Published in: Proceedings of 1994 VLSI Technology Symposium pp. 53 - 54
• Main Authors: Mori, S., Sakagami, E., Yamaguchi, Y., Kamiya, E., Tanimoto, M., Tsunoda, H., Hisatomi, K., Egawa, H., Arai, N., Hiura, Y., Yoshikawa, K., Hashimoto, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1994
• Subjects: Channel hot electron injection; EPROM; Flash memory; Impurities; Isolation technology; Laboratories; Low voltage; Power supplies; Scalability; Semiconductor devices

This paper describes the novel process/device technology for high speed sub-halfmicron flash memories with 0.4 /spl mu/m design rules. Some new structures and operating methods for future flash memories have been proposed. However, the most suitable structure to realize large memory capacity for mag...