High speed sub-halfmicron flash memory technology with simple stacked gate structure cell

• Published in: Proceedings of 1994 VLSI Technology Symposium pp. 53 - 54
• Main Authors: Mori, S., Sakagami, E., Yamaguchi, Y., Kamiya, E., Tanimoto, M., Tsunoda, H., Hisatomi, K., Egawa, H., Arai, N., Hiura, Y., Yoshikawa, K., Hashimoto, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1994
• Subjects: Channel hot electron injection; EPROM; Flash memory; Impurities; Isolation technology; Laboratories; Low voltage; Power supplies; Scalability; Semiconductor devices
• ISBN: 9780780319219; 0780319214
• DOI: 10.1109/VLSIT.1994.324381

This paper describes the novel process/device technology for high speed sub-halfmicron flash memories with 0.4 /spl mu/m design rules. Some new structures and operating methods for future flash memories have been proposed. However, the most suitable structure to realize large memory capacity for magnetic disk replacement will be different from that for fast random access speed for EPROM replacement, flash-memory-embedded logic devices, and other high speed applications. To realize high speed random access operation, conventional NOR-type flash memory technology with CHE program and source erase scheme will be the most suitable because of its simple fabrication process, relatively small cell size, sufficiently high read current, and relatively low operation voltages for program and erase procedures. The low voltage program/erase operation results in high performance peripheral transistors. On the other hand, NAND flash EEPROM will be the most suitable for low-cost large memory capacity applications. This paper, for the first time, demonstrates the scalability of cell gate length down to 0.4 /spl mu/m for simple stacked gate NOR flash cell.< >