Predictability of load/store instruction latencies

Presents a model of coarse grain dataflow execution. The authors present one top down and two bottom up methods for generation of multithreaded code, and evaluate their effectiveness. The bottom up techniques start from a fine-grain dataflow graph and coalesce this into coarse-grain clusters. The to...

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Bibliographic Details
Published inProceedings of the 26th Annual International Symposium on Microarchitecture pp. 139 - 152
Main Authors Abraham, Santosh G., Sugumar, Rabin A., Windheiser, Daniel, Rau, B. R., Gupta, Rajiv
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1993
Subjects
Computer architecture
Computer science
Costs
Delay
Hardware
Hybrid power systems
Parallel processing
Registers
Size measurement
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Summary:Presents a model of coarse grain dataflow execution. The authors present one top down and two bottom up methods for generation of multithreaded code, and evaluate their effectiveness. The bottom up techniques start from a fine-grain dataflow graph and coalesce this into coarse-grain clusters. The top down technique generates clusters directly from the intermediate data dependence graph used for compiler optimizations. The authors discuss the relevant phases in the compilation process. They compare the effectiveness of the strategies by measuring the total number of clusters executed, the total number of instructions executed, cluster size, and number of matches per cluster. It turns out that the top down method generates more efficient code, and larger clusters. However the number of matches per cluster is larger for the top down method, which could incur higher cluster synchronization costs.< >
ISBN:0818652802
9780818652806
DOI:10.1109/MICRO.1993.282750