Carrier confinement in MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructures

• Published in: Technical digest - International Electron Devices Meeting pp. 383 - 386
• Main Authors: Garone, P.M., Venkataraman, V., Sturm, J.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1990
• Subjects: Carrier confinement; MOS devices; Numerical models; Predictive models; Scattering
• ISSN: 0163-1918
• DOI: 10.1109/IEDM.1990.237151

The confinement of carriers in a MOS-gated Ge/sub x/Si/sub 1-x/ heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/Ge/sub x/Si/sub 1-x/ interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the Ge/sub x/Si/sub 1-x/ well, subject to the constraints of surface scattering and processing considerations.< >