Optimizing carry lookahead adders for semicustom CMOS
The authors present a practical method for constructing optimal carry lookahead adders, of width n<or=84. They formulate this design problem as a two-dimensional dynamic program, in which optimization is performed with respect to both adder size and latency. The adders are fast, are modularly bui...
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Published in | [1993] Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems pp. 119 - 122 |
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Main Authors | , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE Comput. Soc. Press
1993
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Subjects | |
Online Access | Get full text |
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Summary: | The authors present a practical method for constructing optimal carry lookahead adders, of width n<or=84. They formulate this design problem as a two-dimensional dynamic program, in which optimization is performed with respect to both adder size and latency. The adders are fast, are modularly built, are relatively easy to lay out, and fully exploit the timing characteristics of CMOS standard cells or gate arrays.< > |
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ISBN: | 9780818634307 0818634308 |
DOI: | 10.1109/GLSV.1993.224466 |