MinMux: a new approach for global minimization of multiplexers in interconnect synthesis

The problem of minimizing interconnection complexity in behavioral level synthesis is considered. In particular, it is assumed that logical connection requirements have already been determined, with a corresponding level of multiplexing implied. The total amount of multiplexing is further reduced by...

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Bibliographic Details
Published in[1993] Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems pp. 132 - 138
Main Authors Wilson, T.C., Garg, M.K., Deadman, R., Halley, B., Banerji, D.K.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1993
Subjects
Application specific integrated circuits
Costs
Integrated circuit interconnections
Iterative algorithms
Iterative methods
Merging
Multiplexing
Scheduling
Very large scale integration
Wires
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Summary:The problem of minimizing interconnection complexity in behavioral level synthesis is considered. In particular, it is assumed that logical connection requirements have already been determined, with a corresponding level of multiplexing implied. The total amount of multiplexing is further reduced by combining connections onto shared path segments, when possible. Using the number of equivalent 2*1 multiplexers as the measure of interconnection complexity, the optimum solution to this problem can be guaranteed. The solution technique uses integer linear programming, preceded by a process that reduces the problem space without compromising optimality. It is shown how to minimize the total number of tristate buffers in a bus implementation.< >
ISBN:9780818634307
0818634308
DOI:10.1109/GLSV.1993.224463