A Fully Integrated 10Gbps Receiver with Adaptive Optical Dispersion Equalizer in 0.13/spl mu/m CMOS

A 10Gbps receiver, containing an adaptive equalizer, a clock and data recovery (CDR), and a demultiplexer, is implemented in 0.13 mum CMOS. By compensating for optical dispersion, this chip recovers transmitted data after 200km of single-mode fiber at BER < 10 -12 . Use of analog equalizer with d...

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Bibliographic Details
Published in2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers pp. 118 - 119
Main Authors Momtaz, A., Chung, D., Kocaman, N., Caresosa, M., Cao, J., Bo Zhang, Fujimori, I.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
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Summary:A 10Gbps receiver, containing an adaptive equalizer, a clock and data recovery (CDR), and a demultiplexer, is implemented in 0.13 mum CMOS. By compensating for optical dispersion, this chip recovers transmitted data after 200km of single-mode fiber at BER < 10 -12 . Use of analog equalizer with digital adaptation garners total power dissipation of 950mW
ISBN:9781424400065
1424400066
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2006.1705338