Parallel encoders for low-density parity-check convolutional codes

Low-density parity-check convolutional codes combine the good bit error rate performance of low-density parity-check block codes with the ability to encode and decode arbitrary lengths of data. This makes them attractive in applications where the data unit to be encoded varies in length. In this pap...

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Bibliographic Details
Published in2006 IEEE International Symposium on Circuits and Systems (ISCAS) p. 4 pp.
Main Authors Bates, S., Ramkrishna Swamy
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
AWGN
Bit error rate
Block codes
Communication standards
Convolutional codes
Decoding
Field programmable gate arrays
Parallel processing
Parity check codes
Throughput
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Summary:Low-density parity-check convolutional codes combine the good bit error rate performance of low-density parity-check block codes with the ability to encode and decode arbitrary lengths of data. This makes them attractive in applications where the data unit to be encoded varies in length. In this paper we discuss the parallelization of encoders for low-density parity-check convolutional code. We then present results to show how this parallelism impacts on the area and throughput of VLSI implementations of these encoders. We show how this technique can be used to implement encoders with throughputs suitable for next-generation communication standards and other high-speed applications
ISBN:0780393899
9780780393899
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2006.1693711