Low power design of H.264 CAVLC decoder

• Published in: 2006 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 4 pp. - 2692
• Main Authors: Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Automatic voltage control; Classification tree analysis; Context modeling; Decoding; Digital video broadcasting; Energy consumption; Entropy coding; Hardware; Throughput; Very large scale integration
• ISBN: 0780393899; 9780780393899
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2006.1693178

In this paper, a low power architecture for realizing the CAVLC decoder is proposed. In traditional VLC decoding algorithms, we could search a level in Huffman coding tree per operation. Therefore, the throughput rate is limited by the searching level. The CAVLC algorithm takes the advantage of the trend among AC coefficients in each block to predict the next codeword. The prediction mechanism can significantly improve the decoding efficiency. Hence, we suggested two efficient approaches, table partitioning and prefix predecoding, to reduce the power consumption in decoding the VLC codes. The proposed low-power CAVLD architecture achieves the real-time requirement for 720p HD (1280times720) format, while the clock is operated at 125 MHz. In simulations, the proposed architecture can reduce about 25% of power consumption in comparison to its counterpart without low power design