A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-/spl mu/m CMOS

• Published in: 48th Midwest Symposium on Circuits and Systems, 2005 pp. 1003 - 1006 Vol. 2
• Main Authors: Heedley, P.L., Dyer, K.C., Matthews, T.W., Isakanian, P., Chuc Thanh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Bandwidth; Capacitors; Circuit topology; Clocks; Copper; Decoding; Feedback; Fingers; Sampling methods; Switches

An 8-b pipelined ADC constructed in 0.13-mum CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125MS/s while consuming 30mW from 1.8-V and 1.2-V supplies. Active area is 0.4mm 2