A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-/spl mu/m CMOS
An 8-b pipelined ADC constructed in 0.13-mum CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125MS/s while consuming 30mW from 1.8-V and 1.2-V supplies. Active area is 0.4mm 2
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Published in | 48th Midwest Symposium on Circuits and Systems, 2005 pp. 1003 - 1006 Vol. 2 |
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Main Authors | , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
2005
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Subjects | |
Online Access | Get full text |
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Summary: | An 8-b pipelined ADC constructed in 0.13-mum CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125MS/s while consuming 30mW from 1.8-V and 1.2-V supplies. Active area is 0.4mm 2 |
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ISBN: | 9780780391970 0780391977 |
ISSN: | 1548-3746 1558-3899 |
DOI: | 10.1109/MWSCAS.2005.1594273 |