APA (7th ed.) Citation

Schaefer, T. (1985). A Transistor-Level Logic-with-Timing Simulator for MOS Circuits. 22nd ACM/IEEE Design Automation Conference, 762-765. https://doi.org/10.1109/DAC.1985.1586031

Chicago Style (17th ed.) Citation

Schaefer, T.J. "A Transistor-Level Logic-with-Timing Simulator for MOS Circuits." 22nd ACM/IEEE Design Automation Conference 1985: 762-765. https://doi.org/10.1109/DAC.1985.1586031.

MLA (9th ed.) Citation

Schaefer, T.J. "A Transistor-Level Logic-with-Timing Simulator for MOS Circuits." 22nd ACM/IEEE Design Automation Conference, 1985, pp. 762-765, https://doi.org/10.1109/DAC.1985.1586031.