A Transistor-Level Logic-with-Timing Simulator for MOS Circuits

VTIsim is a transistor-level simulator for MOS circuits which provides logic simulation together with approximate timing estimates based on layout information. Two novel features enhance the accuracy of simulation: node states are represented as voltages rather than as logic states, and node transit...

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Bibliographic Details
Published in22nd ACM/IEEE Design Automation Conference pp. 762 - 765
Main Author Schaefer, T.J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1985
Subjects
Circuit simulation
Discrete event simulation
Electric resistance
Integrated circuit modeling
Logic circuits
Semiconductor device modeling
Switches
Threshold voltage
Timing
Very large scale integration
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ISBN0818606355
9780818606359
ISSN0738-100X
DOI10.1109/DAC.1985.1586031

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Summary:VTIsim is a transistor-level simulator for MOS circuits which provides logic simulation together with approximate timing estimates based on layout information. Two novel features enhance the accuracy of simulation: node states are represented as voltages rather than as logic states, and node transitions are modeled as voltage ramps rather than as steps taking place at a fixed instant. This paper describes the major features of the simulator, some issues in its design, and the benefits and problems of using it.
ISBN:0818606355
9780818606359
ISSN:0738-100X
DOI:10.1109/DAC.1985.1586031