High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

• Published in: IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005 pp. 151 - 154
• Main Authors: Chunghyun Ryu, Daehyun Chung, Junho Lee, Kwangyong Lee, Taesung Oh, Kim, Joungho
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Capacitance; Coplanar waveguides; Equivalent circuits; Frequency; Integrated circuit interconnections; Packaging; Scattering parameters; Semiconductor device measurement; Silicon; Stacking

In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circui...