High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circui...

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Bibliographic Details
Published inIEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005 pp. 151 - 154
Main Authors Chunghyun Ryu, Daehyun Chung, Junho Lee, Kwangyong Lee, Taesung Oh, Kim, Joungho
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Capacitance
Coplanar waveguides
Equivalent circuits
Frequency
Integrated circuit interconnections
Packaging
Scattering parameters
Semiconductor device measurement
Silicon
Stacking
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Summary:In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circuit model is verified experimentally in frequency and time domains. Furthermore, the high frequency characteristics of the chip-to-chip vertical via are investigated.
ISBN:9780780392205
0780392205
ISSN:2165-4107
DOI:10.1109/EPEP.2005.1563724