A 1V, Ka Band Prescaler with VTControl in 90nm CMOS SOI

This paper presents a static frequency divider in a 90nm PD CMOS SOI process. The divider uses a novel D-latch topology and has an operation range of 8 to 28GHz with maximum sensitivity tuning of plusmn3GHz around 22GHz. The D-latches were implemented with NMOS transistors in R-NMOS logic. A new met...

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Bibliographic Details
Published in2005 IEEE International SOI Conference Proceedings pp. 41 - 43
Main Authors Ionita, R., Sanduleanu, M.A.T., Stikvoort, E., Vladimirescu, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Circuit topology
Clocks
CMOS logic circuits
CMOS process
Coupling circuits
Frequency conversion
Inductors
Latches
Low voltage
Threshold voltage
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Summary:This paper presents a static frequency divider in a 90nm PD CMOS SOI process. The divider uses a novel D-latch topology and has an operation range of 8 to 28GHz with maximum sensitivity tuning of plusmn3GHz around 22GHz. The D-latches were implemented with NMOS transistors in R-NMOS logic. A new method is proposed for tuning the sensitivity curve of the prescaler by controlling the threshold voltage of the transistors. The V T spread due to process variations is compensated too. The V T control shows an improvement of the prescaler sensitivity with forward body-biasing voltages and an increase of the frequency range with reverse body-biasing voltages. At maximum operating frequency, the power consumption of the divider is 60mW (1V supply voltage) and the active area, including buffers, is 350 times 400mum 2
ISBN:0780392124
9780780392120
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.2005.1563527