Ringtree: a VLSI architecture for fast image generation and processing

The authors describe a hardware architecture called Ringtree for 2D geometry generation and processing such as image processing (noise suppression, notch elimination and contour extraction), graphics processing (polygon filing and multiwindowing with nonrectangular windows), and VLSI layout verifica...

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Bibliographic Details
Published in1988 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 801 - 804 vol.1
Main Authors Eo, K.S., Kim, S.S., Kyung, C.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1988
Subjects
Geometry
Graphics
Hardware
Image generation
Image processing
Layout
Noise generators
Tree graphs
Very large scale integration
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Summary:The authors describe a hardware architecture called Ringtree for 2D geometry generation and processing such as image processing (noise suppression, notch elimination and contour extraction), graphics processing (polygon filing and multiwindowing with nonrectangular windows), and VLSI layout verification (design-rule checking). Ringtree consists of a ring memory which is a special rotating frame buffer, an edge painting tree (EPT), which is a polygon rasterizing hardware, and a linear processor array (LPA). The LPA executes a set of basic operations applicable for bit map data manipulation while the EPT generates the bit map data from a set of scanline commands received from host processor. VLSI implementation issues are also discussed for practical display screen size of 1024*1024 pixels, utilizing the Super Tree concept of J. Poulton et al. (1985) for realizing the whole system using identical VLSI chips.< >
DOI:10.1109/ISCAS.1988.15046