A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2/sup nd/-order /spl Delta//spl Sigma/ ADC for WCDMA in 90nm CMOS

A single-amplifier double-sampling second-order /spl Delta//spl Sigma/ ADC with 5-level quantization is implemented in 90nm CMOS. To alleviate the capacitor mismatch issues in double sampling techniques, a single capacitor method is introduced, achieving 63dB peak SNDR and 66dB DR in a 1.94MHz bandw...

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Bibliographic Details
Published inISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005 pp. 170 - 591 Vol. 1
Main Authors Jinseok Koh, Yunyoung Choi, Gomez, G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Capacitors
Circuits
Delta modulation
Energy consumption
Filters
Multiaccess communication
Operational amplifiers
Quantization
Sampling methods
Transfer functions
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Summary:A single-amplifier double-sampling second-order /spl Delta//spl Sigma/ ADC with 5-level quantization is implemented in 90nm CMOS. To alleviate the capacitor mismatch issues in double sampling techniques, a single capacitor method is introduced, achieving 63dB peak SNDR and 66dB DR in a 1.94MHz bandwidth while consuming 1.2mW from a 1.2V supply.
ISBN:0780389042
9780780389045
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1493923