BIFET - A high-performance, bipolar-MOSFET (NPN-nMOS) structure

• Published in: 1972 International Electron Devices Meeting p. 20
• Main Authors: Vora, M.B., Kroell, K., Hegedus, C.L.
• Format: Conference Proceeding
• Language: English
• Published: IRE 1972
• Subjects: Switches
• DOI: 10.1109/IEDM.1972.249237

This paper describes a method of integrating an npn bipolar transistor and an n -channel MOSFET on a silicon wafer. With conventional processes, such integration requires a large number of processing steps. The self-isolation process lends itself nicely to the integration of MOSFET with npn transistors and requires only three diffusions and one thin-oxide growth step. To fabricate a BIFET structure one starts with a p - substrate. The simultaneous diffusion of high-concentration arsenic with low-concentration phosphorus is followed by deposition of a 3µm, 2 ohm-cm layer of p-epitaxy, and then by high-temperature oxidation. Out-diffusion of phosphorus during this oxidation creates an isolated n/n + pocket, over which a base diffusion is made, followed by an n + arsenic emitter diffusion. During this n + diffusion, a source-drain diffusion for MOSFET is also formed over the p-epitaxy. The next step is to open a window for the gate and to grow 500 Å of oxide with phosphosilicate glass passivation. Finally contact holes are opened and metal is deposited.