The address translation unit of the data-intensive architecture (DIVA) system

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as...

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Bibliographic Details
Published inProceedings of the 28th European Solid-State Circuits Conference pp. 767 - 770
Main Authors Herming Chiueh, Draper, J., Mediratta, S., Sondeen, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Bandwidth
Computer architecture
Coprocessors
Data engineering
Integrated circuit interconnections
Memory management
Microprocessors
System buses
System-on-a-chip
Very large scale integration
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Summary:The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system. Thus, performances of pointer-based and sparse-matrix computations as well as multimedia applications are significantly enhanced. A key feature of the DIVA architecture is the address translation mechanism, which supports virtual addressing of application code and data. Instead of prohibitive conventional page tables, DIVA provides a simplified mechanism using segments. In this paper, the design of the address translation unit is presented, and trade-offs in VLSI design including performance, area, and design modulation are also discussed.