A novel driver architecture capable of driving high capacitive loads for sub-half micron technologies

The purpose of this paper is to present a new CMOS compatible driver which overcomes certain limitations of the conventional CMOS circuits. The proposed driver has very low fan-in (about 50% reduction) and, as it will be demonstrated, is very efficient for high capacitive loads. These benefits are o...

Full description

Saved in:
Bibliographic Details
Published inProceedings of the 23rd European Solid-State Circuits Conference pp. 112 - 115
Main Authors Bouras, I., Papadas, C., Moreau, J., Katsafouros, S.G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1997
Subjects
BiCMOS integrated circuits
Capacitance
CMOS technology
Driver circuits
Microelectronics
MOS devices
MOSFET circuits
Power dissipation
Research and development
Voltage
Online AccessGet full text

Cover

More Information
Summary:The purpose of this paper is to present a new CMOS compatible driver which overcomes certain limitations of the conventional CMOS circuits. The proposed driver has very low fan-in (about 50% reduction) and, as it will be demonstrated, is very efficient for high capacitive loads. These benefits are obtained without any excess of power dissipation compared to the standard CMOS solution. It will also be shown that this basic architecture is applicable to BiCMOS technology. The operation of the proposed drivers is attributed to a Deep Depletion Condition phenomenon, present in sub-half micron CMOS/BiCMOS technologies, for input pulses with fast rise times.