4.0GHz 0.18/spl mu/m CMOS PLL based on an interpolate oscillator

• Published in: Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 pp. 100 - 103
• Main Authors: Gebara, F.H., Schaub, J.D., Drake, A.J., Nowka, K.J., Brown, R.B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Delay effects; Digital circuits; Frequency; Interpolation; Inverters; Jitter; Phase locked loops; Pipelines; Tuning; Voltage-controlled oscillators

Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which i...