4.0GHz 0.18/spl mu/m CMOS PLL based on an interpolate oscillator

Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which i...

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Bibliographic Details
Published inDigest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 pp. 100 - 103
Main Authors Gebara, F.H., Schaub, J.D., Drake, A.J., Nowka, K.J., Brown, R.B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Delay effects
Digital circuits
Frequency
Interpolation
Inverters
Jitter
Phase locked loops
Pipelines
Tuning
Voltage-controlled oscillators
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Summary:Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which is capable of clocking even the most demanding logic families. Experimental results, from a TSMC 0.18/spl mu/m process, show oscillator frequencies as high as 4.6GHz and rms jitter values of less then 1.25ps. Additionally, the PLL was able to lock to form a 4GHz output signal. These results are among the best published to date in this process.
ISBN:9784900784017
490078401X
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2005.1469343