Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded me...

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Bibliographic Details
Published inDigest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 pp. 38 - 39
Main Authors Ranica, R., Villaret, A., Malinge, P., Gasiot, G., Mazoyer, P., Roche, P., Candelier, P., Jacquet, F., Masson, P., Bouchakour, R., Fournel, R., Schoellkopf, J.P., Skotnicki, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
CMOS logic circuits
CMOS process
CMOS technology
Error analysis
Fabrication
Impact ionization
Logic devices
Logic programming
Random access memory
Testing
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Summary:A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.
ISBN:4900784001
9784900784000
ISSN:0743-1562
DOI:10.1109/.2005.1469203