A low power embedded dataflow coprocessor

Power consumption has become one of the most important concerns in microprocessor design. However, the potential for further power-saving in microprocessors with a conventional architecture is limited because of their unified architectures and mature low-power techniques. An alternative way is propo...

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Bibliographic Details
Published inIEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) pp. 246 - 247
Main Authors Yijun Liu, Furber, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Bandwidth
Computer architecture
Coprocessors
Data processing
Energy consumption
Engines
Hardware
Iterative decoding
Microprocessors
Reduced instruction set computing
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ISBN9780769523651
076952365X
ISSN2159-3469
DOI10.1109/ISVLSI.2005.9

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Summary:Power consumption has become one of the most important concerns in microprocessor design. However, the potential for further power-saving in microprocessors with a conventional architecture is limited because of their unified architectures and mature low-power techniques. An alternative way is proposed in this paper to save power - embedding a dataflow coprocessor in a conventional RISC processor. The dataflow coprocessor is designed to execute short code segments very efficiently. The primary experimental results show that the dataflow coprocessor can increase the power efficiency of a RISC processor by an order of magnitude.
ISBN:9780769523651
076952365X
ISSN:2159-3469
DOI:10.1109/ISVLSI.2005.9