The chip-multithreading architecture and parallel optical interconnects

Tens of terabits-per-second bandwidth will be required for revolutionary chip-multithreading (CMT) architectures. In this presentation, we will review the technical challenges for electrical signaling and discuss how parallel optical interconnects could be valuable in CMT architectures.

Saved in:
Bibliographic Details
Published inDigest of the LEOS Summer Topical Meetings Biophotonics/Optical Interconnects and VLSI Photonics/WBM Microcavities, 2004 p. 2 pp.
Main Authors Huang, D., Sze, T., Krishnamoorthy, A.V., Alamo, A.D., Beckman, D., Fazelpour, S., Davidson, H., Cooley, J., Lytel, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2004
Subjects
Bandwidth
Clocks
Crosstalk
Jitter
Multithreading
Optical interconnections
Packaging
Pins
Throughput
Yarn
Online AccessGet full text

Cover

More Information
Summary:Tens of terabits-per-second bandwidth will be required for revolutionary chip-multithreading (CMT) architectures. In this presentation, we will review the technical challenges for electrical signaling and discuss how parallel optical interconnects could be valuable in CMT architectures.
ISBN:0780383060
9780780383067
ISSN:1099-4742
2376-8614
DOI:10.1109/LEOSST.2004.1338714