Empirical evaluation of timing and power in resonant clock distribution

• Published in: 2004 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 2; pp. II - 249
• Main Authors: Juang-Ying Chueh, Ziesler, C.H., Papaefthymiou, M.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Capacitance; Clocks; Energy consumption; Flip-flops; Frequency; Power dissipation; Power generation; Resonance; Timing; Voltage
• ISBN: 078038251X; 9780780382510
• DOI: 10.1109/ISCAS.2004.1329255

Resonant clocking is an attractive alternative to conventional clock distribution due to its significant potential for reducing clocking power. Typically, resonant clock systems rely on sinusoidal clock signals to synchronize flip-flops. Understanding clock skew and power is particularly important in these systems, because unlike their conventional counterparts, resonant clock networks do not use any buffers. We have performed a simulation study of clock skew and power in resonant H-shape clock distribution networks with sinusoidal waveforms. Focusing on the impact of width, spacing, and loading on clock skew, our study suggests practical design guidelines for low-skew resonant clocking. Our results show that compared to conventional clocking, properly designed resonant clocking yields comparable or better skew. Furthermore, simultaneous improvements in skew and power of resonant clock are possible through width scaling. Our experiments also confirm the theoretical prediction that energy dissipation in resonant clock networks scales with RC/T, where RC is the load of the network, and T is the clock period.