The mechanical planarization of interlevel dielectrics for multilevel interconnect applications

A description is given of the application of mechanical planarization to the interlevel dielectric (ILD) of a multilevel interconnect system. Experimental results obtained from large 80K, two-level metal CMOS gate arrays (0.7 cm/sup 2/) having mechanically planarized ILD indicated leveling lengths o...

Full description

Saved in:
Bibliographic Details
Published inSeventh International IEEE Conference on VLSI Multilevel Interconnection pp. 438 - 440
Main Authors Thomas, M.E., Sekigahama, S., Renteln, P., Pierce, J.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1990
Subjects
Area measurement
Dielectrics
Fabrication
Glass
Image generation
Planarization
Resists
Smoothing methods
Surface topography
Ultra large scale integration
Online AccessGet full text

Cover

More Information
Summary:A description is given of the application of mechanical planarization to the interlevel dielectric (ILD) of a multilevel interconnect system. Experimental results obtained from large 80K, two-level metal CMOS gate arrays (0.7 cm/sup 2/) having mechanically planarized ILD indicated leveling lengths on the order of 0.5 cm and excellent via functionality. Surface leveling with variations of less than 200 AA was readily achieved over the whole gate array die. No detrimental effects were observed in a fully functional die when compared with devices using sacrificial spin-on glass. The results of this study indicate that mechanical planarization will make a critical contribution to the fabrication of ULSI devices having 0.25- mu m interconnect feature sizes.< >
DOI:10.1109/VMIC.1990.127923