Security wrappers and power analysis for SoC technology

• Published in: First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721) pp. 162 - 167
• Main Authors: Gebotys, C.H., Zhang, Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Algorithm design and analysis; Application software; Circuits; Communication system security; Design methodology; Hardware; Network-on-a-chip; Power system security; Protection; System-on-a-chip
• ISBN: 1581137427; 9781581137422
• DOI: 10.1109/CODESS.2003.1275277

Future wireless Internet enabled services will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resistance to bus probing attacks, power/EM attacks on cores and network snooping attacks by malicious code are relevant. This paper presents a methodology for security on NoC at both the network level (or transport layer) and at the core level (or application layer) is proposed. For the first time a low cost security wrapper design is presented, which prevents unencrypted keys from leaving the cores and NoC. This is crucial to prevent untrusted software on or off the NoC from gaining access to keys. At the core level (application layer) power analysis attacks are examined for the first time for parallel and adiabatic architectural cores. With the emergence of secure IP cores in the market, a security methodology for designing NoCs is crucial for supporting future wireless Internet enabled devices.