Highly manufacturable sub-50 nm high performance CMOSFET using real damascene gate process

We demonstrate highly manufacturable sub-50 nm CMOSFETs using 'real' damascene gate process without dummy gate formation, which has structural merits in scaling resulting from locally implanted channel. The fabricated sub-50 nm CMOSFETs show the excellent suppression of short channel effec...

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Published in2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) pp. 147 - 148
Main Authors Chang-Woo Oh, Sung-Ho Kim, Chang-Sub Lee, Jeong-Dong Choe, Shin-Ae Lee, Sung-Young Lee, Kyung-Hwan Yeo, Hye-Jin Jo, Eun-Jung Yoon, Sang-Jin Hyun, Donggun Park, Kinam Kim
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Boron
CMOSFETs
Dielectrics
Doping
Fabrication
Manufacturing processes
MOS devices
MOSFET circuits
Plasma measurements
Plasma properties
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Summary:We demonstrate highly manufacturable sub-50 nm CMOSFETs using 'real' damascene gate process without dummy gate formation, which has structural merits in scaling resulting from locally implanted channel. The fabricated sub-50 nm CMOSFETs show the excellent suppression of short channel effect due to the locally implanted channel and the outstanding current drivability, 810 /spl mu/A//spl mu/m for nMOS and 424 /spl mu/A//spl mu/m for pMOS at V/sub DD/=1.0 V and I/sub OFF/=100 nA//spl mu/m. In particular, the pMOS performance is comparable to the state-of-the-art result.
ISBN:9784891140335
489114033X
DOI:10.1109/VLSIT.2003.1221128