Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

• Published in: 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) pp. 21 - 22
• Main Authors: Tsai, W., Ragnarsson, L., Chen, P.J., Onsia, B., Carter, R.J., Cartier, E., Young, E., Green, M., Caymax, M., De Gendt, S., Heyns, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Annealing; Capacitors; Chemical processes; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Leakage current; MOS devices; MOSFET circuits; Tin

Chemical oxide scaling by modulating ozone concentration is used to produce SiO/sub x/ interfaces with thickness as low as 0.3 nm for HfO/sub 2/ dielectrics. Poly NMOS capacitors and conventional self-aligned transistors down to 65 nm gate lengths with final EOT ranged from 1.2-1.8 nm were obtained....