Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

Chemical oxide scaling by modulating ozone concentration is used to produce SiO/sub x/ interfaces with thickness as low as 0.3 nm for HfO/sub 2/ dielectrics. Poly NMOS capacitors and conventional self-aligned transistors down to 65 nm gate lengths with final EOT ranged from 1.2-1.8 nm were obtained....

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Published in2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) pp. 21 - 22
Main Authors Tsai, W., Ragnarsson, L., Chen, P.J., Onsia, B., Carter, R.J., Cartier, E., Young, E., Green, M., Caymax, M., De Gendt, S., Heyns, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Annealing
Capacitors
Chemical processes
Hafnium oxide
High K dielectric materials
High-K gate dielectrics
Leakage current
MOS devices
MOSFET circuits
Tin
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Summary:Chemical oxide scaling by modulating ozone concentration is used to produce SiO/sub x/ interfaces with thickness as low as 0.3 nm for HfO/sub 2/ dielectrics. Poly NMOS capacitors and conventional self-aligned transistors down to 65 nm gate lengths with final EOT ranged from 1.2-1.8 nm were obtained. Sputtered TiN gate on the identical stacks yielded 0.82 nm EOT on NMOS devices using scaled chemical oxide interface with leakage current of 10/sup -3/ A/cm/sup -2/. CV hysteresis of TiN/HfO/sub 2/ was observed to decrease by an order of magnitude from the as deposited value to <10 mV after a 900/spl deg/C N/sub 2/ anneal.
ISBN:9784891140335
489114033X
DOI:10.1109/VLSIT.2003.1221066