Built-in self-test in a 24 bit floating point digital signal processor

• Published in: Proceedings. International Test Conference 1990 pp. 880 - 885
• Main Authors: Sakashita, N., Sawai, H., Teraoka, E., Fujiyama, T., Kengaku, T., Shimazu, Y., Tokuda, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1990
• Subjects: Arithmetic; Automatic testing; Built-in self-test; Costs; Digital signal processing; Digital signal processing chips; Digital signal processors; Large scale integration; Research and development; Very large scale integration
• ISBN: 9780818690648; 081869064X
• DOI: 10.1109/TEST.1990.114106

The authors describe a built-in self-test (BIST) method implemented in a 24-b floating-point digital signal processor (DSP) using pseudorandom patterns. By use of only one pair- of LFSRs (linear feedback shift registers) and 253 words of normal instruction, 95% of the functional blocks are self-tested. The number of the test vectors is 35 million. However, the entire BIST takes only 2.6 s for the test, owing to the fast machine cycle time of 75 ns. The overhead of the test hardware is only 2.0% of the die size. The evaluation results show that a BIST is very useful for computationally intensive VLSI processors, such as a DSP.< >