View of Charge Carrier Mobility in Lateral Gates Junction-Less Transistor

• Published in: Proceedings of the ... IEEE Conference on Nanotechnology pp. 46 - 51
• Main Authors: Larki, Farhad, Dehzangi, Arash
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13.07.2025
• Subjects: effective mass; hole mobility; hole velocity; Impurities; Junctionless transistor; lateral gate; Logic gates; Phonons; Potential well; Rough surfaces; Scattering; Simulation; Surface roughness; Transistors; Voltage
• ISSN: 1944-9380
• DOI: 10.1109/NANO63165.2025.11113741

We study the charge carrier mobility of a p-type lateral gates junction-less silicon transistor through experimental and simulation results. The device features a specific structure that lacks a gate oxide layer, no junction with a low doping profile for the channel, aiming to suppress impurity scattering, phonon scattering and surface roughness scattering to enhance the mobility of the carries. The device was simulated by 3D-TCAD Sentaurus and simulation results were compared with experimental for transconductance and drain conductance. The fabricated device exhibits an on-off current ratio of 10 6 between 0 to +2 V. Moreover, the effect of channel width and the gate gap on the velocity and mobility variation of the majority carriers have also been investigated. Based on the simulation data, by decreasing the gate gap into a few nanometers, the quantum confinement in the lateral direction becomes stronger. This alters the valence band structure, increasing the effective mass of the holes and confines holes more strongly in the lateral direction.