A Low-Power Reduced Error Lower Part-OR Adder for Multimedia Applications

• Published in: 2025 International Conference on Electronics, AI and Computing (EAIC) pp. 1 - 6
• Main Authors: Gupta, Garima, Garg, Bharat, Bansal, Manu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05.06.2025
• Subjects: Adder; Adders; Approximate design; Complexity theory; Computer architecture; Delay; Delays; Detectors; Error tolerant applications; Logic; Low Power; Measurement; Multimedia computing; Performance evaluation; Signal processing
• DOI: 10.1109/EAIC66483.2025.11101480

With the use of multimedia applications, machine learning, and signal processing, approximate computing has become increasingly popular in the pursuit of power-efficient and high-performance architectures for mobile devices. The arithmetic unit is the key component that determines the performance of the overall design. Therefore, in this paper, a novel low-power reduced error lower part-OR adder (RELOA) is proposed. In the proposed architectures, the input bits are divided into three parts, and the sum is computed accurately or approximately based on their significance in the overall sum. The sum of the most significant bits is calculated accurately to have better design metrics, while the least significant bits are approximately to reduce implementation complexity. The proposed architecture offers 16% less power and 9.37% reduction in error metric over existing adders while maintaining a similar delay. Additionally, when processing digital images, the proposed architecture displays good image quality comparable to existing approximate adders.