Emerging Vertical GaN-on-Silicon Devices for Next Generation Power Electronics

• Published in: 2025 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) p. 1
• Main Author: Medjdoub, Farid
• Format: Conference Proceeding
• Language: English
• Published: IEEE 21.04.2025
• Subjects: Avalanche breakdown; Breakdown voltage; Logic gates; Next generation networking; Optimization; Power electronics; Reliability; Silicon; Substrates; Thermal expansion
• DOI: 10.1109/VLSITSA64674.2025.11046979

Although promising and qualified up to 650 V voltage operation, lateral GaN HEMT devices are subject to severe limitations for higher voltage applications such as a large device size, surface trap related reliability concerns or the absence of avalanche breakdown due to the peak electric field at the gate vicinity. This led to vertical GaN development, potentially enabling to overcome all the above-mentioned issues. State-of-the-art vertical GaN devices are fabricated on bulk GaN substrates owing to the reduced dislocation density and low impurity concentrations. However, native GaN substrates are prohibitively expensive, and only available in rather small size. In this talk, we will describe a unique approach and current status of GaN-based fully vertical devices grown on large diameter silicon substrate. Despite the common belief about the limited drift layer thickness or wafer diameter due to the large mismatch in coefficient of thermal expansion (CTE) between Si and GaN, we will show that a local substrate removal with suitable related growth and process optimization enabled outstanding initial achievements such as extremely low on-resistance in 1200 V-class fully vertical pn diodes with avalanche breakdown capability and high on-state current capability.