Tutorial: Circuit Design using FinFETs

• Published in: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Vol. TUTORIAL; pp. 1 - 81
• Main Author: Sheu, Bing
• Format: Conference Proceeding
• Language: English
• Published: IEEE 17.02.2013
• Subjects: 2013; bing sheu; circuit design using finfets; Circuit synthesis; Electrostatic discharges; FinFETs; Layout; Research and development; short courses and tutorials; Solid modeling; Solid state circuits; sscs; Sun; Tutorials; Very large scale integration
• ISBN: 9781467345156; 1467345156
• ISSN: 0193-6530
• DOI: 10.1109/ISSCC12623.2013.11005763

"After HKMG, FinFETs are a powerful yet disruptive technology to enable continuous scaling following Moore's law. The disruptive nature arises from both the 3D structure and the quantization on width choice. FinFETs require new design skills to trade-off among PPA (power-performance-area) and to conduct circuit-process co-optimization. Salient advantages of FinFETs include: increased driving capability per footprint area, better control on short-channel effect, subthreshold slope, and less requirement on channel doping. Thus, threshold voltage can be reduced, which enables a reduction in supply voltage and thus power consumption or increase of performance speed. The tutorial will focus on critical issues of FinFET design: It starts with a crisp comparison of planar vs. 3D FinFET devices and the associated SPICE modeling. Next, logic design is presented, including effects on standard cells, I/O circuitry, and ESD. Then, the subjects of SRAM and analog/mixed-signal design are treated in detail. Digital chip-level design that requires methodology enhancement and new CAD tool features are carefully discussed. The tutorial will enable CMOS designers to systematically comprehend circuit design using FinFETs."