Dynamic Characterization of Proposed SRAM Cell at 16nm Technology

The paper offers an in-depth analysis and design assessment of SRAM cells, focusing on important performance indicators. The article starts off with a summary of memory types, emphasizing the importance of SRAM in a variety of applications. The paper investigates the merits and demerits of multiple...

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Bibliographic Details
Published in2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP) pp. 1 - 6
Main Authors Shukla, Anubhav, Shrivastava, Shreshth, Saran, Sanaskar, Singh, Gurjinder, Dhiman, Gaurav
Format Conference Proceeding
LanguageEnglish
Published IEEE 08.08.2024
Subjects
Computer architecture
Delays
Focusing
Microprocessors
Noise
Power Consumption
Power Delay Product (PDP)
Power demand
Propagation Delay
SRAM
SRAM cells
Stability analysis
Topology
Transistors
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Summary:The paper offers an in-depth analysis and design assessment of SRAM cells, focusing on important performance indicators. The article starts off with a summary of memory types, emphasizing the importance of SRAM in a variety of applications. The paper investigates the merits and demerits of multiple SRAM cell topologies for 16nm technology. In order to assess the suggested 9T cell against other SRAM designs that are currently in use, its power delay product, power consumption, and overall delay have all been examined. The results of the simulation show that although the 9T SRAM cell's delay is noticeably less, it consumes more power than other alternative technologies. In a comparison analysis, the performance of the proposed 9T SRAM cell is compared with that of 6T, 7T, and 10T SRAM cells at 16nm technology.
DOI:10.1109/ICECSP61809.2024.10698273