An Active G-Band Frequency Doubler with High 3rd and 4th Harmonic Suppression in 90-nm CMOS Process

This paper presented a 158-204 GHz frequency multiplier with 3 rd and 4 th harmonic suppression in 90-nm CMOS technology. A push-push doubler topology is implemented in this circuit. The W-band differential signal is made by Marchand balun. In order to achieve the goal of 4th harmonic suppression, a...

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Bibliographic Details
Published in2024 49th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz) pp. 1 - 2
Main Authors Lai, Chih-Hsueh, Wang, Yunshan, Chiong, Chau-Ching, Wang, Huei
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2024
Subjects
Baluns
Bandwidth
Chebyshev approximation
CMOS process
doubler
Frequency conversion
frequency multiplier
G-band
Harmonics suppression
Low-pass filters
Power generation
Power harmonic filters
Topology
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Summary:This paper presented a 158-204 GHz frequency multiplier with 3 rd and 4 th harmonic suppression in 90-nm CMOS technology. A push-push doubler topology is implemented in this circuit. The W-band differential signal is made by Marchand balun. In order to achieve the goal of 4th harmonic suppression, a Chebyshev filter is utilized at the output of the doubler core. The doubler is operated at class B for the highest G m2 . The conversion gain of the frequency doubler is -10dB to -7.6dB when the input power is 10dBm. The 3 rd and 4 th harmonic suppression is greater than 20 and 23dB.
ISSN:2162-2035
DOI:10.1109/IRMMW-THz60956.2024.10697909