Image Processing on the Edge using an Entry-Level FPGA

This paper explores the application of FPGA programmable structures in the field of digital image signal processing (ISP). FPGAs offer high flexibility, speed and parallelism, making them ideal for general digital signal processing (DSP), as well as specific ISP tasks. The paper utilizes standard IS...

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Bibliographic Details
Published in2024 International Symposium ELMAR pp. 367 - 370
Main Authors Zunic, Armin, Sokic, Emir, Osmic, Nedim, Vrce, Isam, Salihbegovic, Almir
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.09.2024
Subjects
Acceleration
Digital signal processing
Field programmable gate arrays
FPGA
Hardware
Image edge detection
ISP
lOT
Optimization
Parallel processing
Parallelism
Real-time systems
Signal processing algorithms
Visualization
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Summary:This paper explores the application of FPGA programmable structures in the field of digital image signal processing (ISP). FPGAs offer high flexibility, speed and parallelism, making them ideal for general digital signal processing (DSP), as well as specific ISP tasks. The paper utilizes standard ISP algorithms such as morphological operations, filtering and edge detection to compare practical implementations of FPGA and CPU-based compute engines. Through illustrative examples and empirical results, we demonstrate the distinct advantages of employing FPGA for these use-cases, and contrast them with traditional CPU approaches, clearly showing FPGA capacity to significantly accelerate execution. The challenges that arise from resource-limited IOT-class hardware configurations are highlighted in the paper, namely resource optimization, memory management and maximal frequency.
ISSN:2835-3781
DOI:10.1109/ELMAR62909.2024.10694571